______________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the ds4402 and ds4404 contain two and four i 2 c adjustable current dacs, respectively, that are eachcapable of sinking or sourcing current. each output has 31 sink and 31 source settings that are programmed by the i 2 c interface. external resistors set the full-scale range and step size of each output. applications power-supply adjustmentpower-supply margining adjustable current sink or source features ? two (ds4402) or four (ds4404) current dacs ? full-scale range for each dac determined byexternal resistors ? 31 settings each for sink and source modes ? i 2 c-compatible serial interface ? two three-level address pins allow ninedevices on same i 2 c bus ? small package (14-pin tdfn) ? -40? to +85? temperature range ? 2.7v to 5.5v operation ds4402/ds4404 two/four-channel, i 2 c adjustable current dac dc/dc converter fb out sdascl a0 a1 out0out1 gnd r fs0 r fs1 4.7k 4.7k v cc v cc v out0 fs0 fs1 r 0b r 0a ds4402 dc/dc converter fb out v out1 r 1b r 1a typical operating circuit ordering information 19-4641; rev 3; 5/09 + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. * ep = exposed pad. part temp range pin-package ds4402 n+ -40c to +85c 14 tdfn-ep* ds4402n+t&r -40c to +85c 14 tdfn-ep* ds4404 n+ -40c to +85c 14 tdfn-ep* ds4404n+t&r -40c to +85c 14 tdfn-ep* tdfn top view 24 5 1311 10 v cc a1out1 scl fs3 (n.c.)fs2 (n.c.) *exposed pad ( ) indicates for ds4402 only. 1 + 14 out3 (n.c.)out2 (n.c.) sda 3 12 gnd 6 9 a0 fs1 7 8 out0 fs0 ds4404/ ds4402 *ep (3mm 3mm 0.8mm) pin configuration downloaded from: http:///
ds4402/ds4404 two/four-channel, i 2 c adjustable current dac 2 ______________________________________________________________________ absolute maximum ratings recommended operating conditions(t a = -40? to +85?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc , sda, and scl relative to ground.............................................-0.5v to +6.0v voltage range on a0, a1, fs0, fs1, fs2, fs3, out0, out1, out2, and out3 relative to ground ................-0.5v to (v cc + 0.5v) (not to exceed 6.0v.) operating temperature range ...........................-40? to +85? storage temperature range .............................-55? to +125? soldering temperature .....................................refer to ipc/jedec j-std-020 specification parameter smbol conditions min tp max units supply voltage v cc (note 1) 2.7 5.5 v input logic 1 (sda, scl, a0, a1) v ih 0.7 x v cc v cc + 0.3 v input logic 0 (sda, scl, a0, a1) v il -0.3 0.3 x v cc v dc electrical characteristics(v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter smbol conditions min tp max units ds4402 500 supply current i cc v cc = 5.5v (note 2) ds4404 500 a input leakage (sda, scl) i il v cc = 5.5v 1 a output leakage (sda) i l 1 a v ol = 0.4v 3 output current low (sda) i ol v ol = 0.6v 6 ma address input resistors r in 240 k reference voltage v ref 1.23 v i/o capacitance c i/o 10 pf output current characteristics(v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter smbol conditions min tp max units output voltage for sinking current v out:sink (note 3) 0.5 v cc v output voltage for sourcing current v out:source (note 3) 0 v cc - 0.5 v full-scale sink output current i out:sink (note 3) 0.5 2.0 ma full-scale source output current i out:source (note 3) -2.0 -0.5 ma output-current full-scale accuracy i out:fs +25c, v cc = 4.0v; using ideal r fs resistor; v out:sink = 0.5v; v out:source = v cc - 0.8v 2.5 5.0 % output-current temperature drift i out:tc (note 4) 70 ppm/c downloaded from: http:///
ds4402/ds4404 two/four-channel, i 2 c adjustable current dac _____________________________________________________________________ 3 note 1: all voltages with respect to ground. currents entering the ic are specified positive, and currents exiting the ic are negative. note 2: supply current specified with all outputs set to zero current setting with all inputs (except a1 and a0, which can be open) driven to well-defined logic levels. sda and scl are connected to v cc . excludes current through r fs resistors (i rfs ). total current including i rfs is i cc + (2 x i rfs ). note 3: the output-voltage full-scale current ranges must be satisfied to ensure the device meets its accuracy and linearity specifications. note 4: temperature drift excludes drift caused by external resistor. note 5: differential linearity is defined as the difference between the expected incremental current increase with respect to positionand the actual increase. the expected incremental increase is the full-scale range divided by 31. note 6: integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.the expected value is a straight line between the zero and the full-scale values proportional to the setting. note 7: timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c standard-mode timing. note 8: c b ?otal capacitance of one bus line in pf. output current characteristics (continued)(v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter smbol conditions min tp max units output-current power-supply rejection ratio dc 0.33 %/v output leakage current at zero current setting i zero -1 +1 a output-current differential linearity dnl (note 5) 0.5 lsb output-current integral linearity inl (note 6) 1 lsb i 2 c ac electrical characteristics (v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units scl clock frequency f scl (note 7) 0 400 khz bus free time between stopand start conditions t buf 1.3 ? hold time (repeated) startcondition t hd:sta 0.6 ? low period of scl t low 1.3 ? high period of scl t high 0.6 ? data hold time t dh:dat 0 0.9 ? data setup time t su:dat 100 ns start setup time t su:sta 0.6 ? sda and scl rise time t r (note 8) 20 + 0.1c b 300 ns sda and scl fall time t f (note 8) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 ? sda and scl capacitive loading c b (note 8) 400 pf downloaded from: http:///
ds4402/ds4404 two/four-channel, i 2 c adjustable current dac 4 ______________________________________________________________________ v cc v cc r fs0 r fs1 r fs2 r fs3 sda scl a1 a0 gnd fs0 fs1 out1 out0 current dac0 f8h f9h source or sink mode fs2 out2 fs3 out3 current dac3 31-positions each for sink and source mode fah fbh ds4402/ds4404 ds4404 current dac1 current dac2 i 2 c-compatible serial interface figure 1. functional diagram pin description pin ds4404 ds4402 name function 1 1 sda i 2 c serial data. input/output for i 2 c data. 2 2 scl i 2 c serial clock. input for i 2 c clock. 3 3 gnd ground 4 fs3 5 fs2 6 6 fs1 7 7 fs0 full-scale calibration input. a resistor to ground on these pins deter mines the full-scale current for each output. fs0 controls out0, fs1 controls out1, etc. (ds4402 has only two inputs: fs0 and fs1.) 8 8 out0 10 10 out1 12 out2 14 out3 current output. sinks or sources the current determined by the i 2 c interface and the resistance connected to fsx. (ds 4402 has only two outputs: out0 and out1.) 9, 11 9, 11 a0, a1 address select inputs. tri-level inputs (v cc , gnd, n.c.) determine the i 2 c slave address. see the detailed description section for the nine available device addresses. 13 13 v cc power supply 4, 5, 12, 14 n.c. no connection ep exposed pad. leave unconnected or connect to gnd. downloaded from: http:///
detailed description the ds4402/ds4404 contain two/four i 2 c adjustable current sources (figure 1) that are each capable ofsinking and sourcing current. each output has 31 sink and 31 source settings that are programmed through the i 2 c interface. the full-scale ranges (and corre- sponding step sizes) of the outputs are determined byexternal resistors that adjust the output currents over a 4:1 range. the formula to determine the external resis- tor values (r fs ) for each of the outputs is given by: equation 1: r fs = (v ref / i fs ) x (31 / 4) where i fs = desired full-scale current on power-up, the ds4402/ds4404 output zero current.this is done to prevent it from sinking or sourcing an incorrect current before the system host controller has had a chance to modify the device? setting. as a source for biasing instrumentation or other cir- cuits, the ds4402/ds4404 provide a simple and inex- pensive current source with an i 2 c interface for control. the adjustable full-scale range allows the application toget the most out of its 5-bit sink or source resolution. when used in adjustable power-supply applications (see the typical operating circuit ), the ds4402/ds4404 do not affect the initial power-up supply voltage becauseit defaults to providing zero output current on power-up. as it sources or sinks current into the feedback voltage node, it changes the amount of output voltage required by the regulator to reach its steady state operating point. by using the external resistor to set the output current range, the devices provide flexibility for adjusting the impedances of the feedback network or the range over which the power supply can be controlled or margined. i 2 c slave address the ds4402/ds4404 respond to one of nine i 2 c slave addresses determined by the two tri-level addressinputs. the three input states are connected to v cc , connected to ground, or disconnected. to sense thedisconnected state (figure 2), the address inputs have weak internal resistors that pull the pins to mid-supply. table 1 lists the slave address determined by theaddress input combinations. ds4402/ds4404 two/four-channel, i 2 c adjustable current dac _____________________________________________________________________ 5 table 1. slave addresses a1 a0 slave address (hexadecimal) gnd gnd 90h gnd v cc 92h v cc gnd 94h v cc v cc 96h n.c. gnd 98h n.c. v cc 9ah gnd n.c. 9ch v cc n.c. 9eh n.c. n.c. a0h a0 a1 i 2 c address decode r in r in v cc r in r in figure 2. i 2 c address inputs downloaded from: http:///
ds4402/ds4404 memory organization to control the ds4402/ds4404? current sources, writeto the memory addresses listed in table 2. the format of each output control register is given by: where: example: i fs0 = 800?, and register f8h is written to a value of 92h. calculate the value of external resistancerequired, and the magnitude of the output current with this register setting. r fs = (v ref / 800?) x (31 / 4) = 11.9k the msb of the output register is 1, so the output issourcing the value corresponding to position 12h (18 decimal). the magnitude of the output current is equal to: 800? x (18 / 31) = 465? i 2 c serial interface description i 2 c definitions the following terminology is commonly used to describei 2 c data transfers: master device: the master device controls the slave devices on the bus. the master device generates sclclock pulses, start and stop conditions. slave devices: slave devices send and receive data at the master? request.bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and intheir logic-high states. when the bus is idle it often initi- ates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave.transitioning sda from high to low while scl remains high generates a start condition. see figure 3 for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioningsda from low to high while scl remains high generates a stop condition. see figure 3 for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data trans-fer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a spe- cific memory address to begin a data transfer. a repeat- ed start condition is issued identically to a normal start condition. see figure 3 for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid andunchanged during the entire high pulse of scl, plus the setup and hold time requirements (figure 3). data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount ofsetup time (figure 3) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses, including when it is reading bits from the slave. two/four-channel, i 2 c adjustable current dac 6 ______________________________________________________________________ msb lsb sxxd 4 d 3 d 2 d 1 d 0 bit name function power-on default s sign bit determines if dac sources or sinks current. for sink s = 0, for source s = 1. 0b x reserved reserved. both bits readzero. 00b d x data 5-bit data word controllingdac output. setting 00000b outputs zero current regardless of the state of the sign bit. 00000b table 2. memory addresses memory address (hexadecimal) current source f8h out0 f9h out1 fah* out2* fbh* out3* *only for ds4404. downloaded from: http:///
acknowledgement (ack and nack): an acknowledge- ment (ack) or not acknowledge (nack) is always theninth bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmit- ting a zero during the ninth bit. a device performs a nack by transmitting a one during the ninth bit. timing for the ack and nack is identical to all other bit writes (figure 4). an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of information transferred from the master to the slave (most significantbit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the master are done according to the bit-write definition, and the acknowledgement is read using the bit-read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nackfrom the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to ter- minated communication so the slave will return control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately follow-ing a start condition. the slave address byte contains the slave address in the most significant 7 bits and ther/ w bit in the least significant bit. the ds4402/ds4404s slave address is determined by the state of the a0 and a1address pins. table 1 describes the addresses corre- sponding to the state of a0 and a1. when the r/ w bit is 0 (such as in a0h), the master is indicating it will write data to the slave. if r/ w = 1 (a1h in this case), the master is indicating it wants to readfrom the slave. if an incorrect slave address is written, the ds4402/ds4404 assume the master is communi- cating with another i 2 c device and ignore the commu- nication until the next start condition is sent.memory address: during an i 2 c write operation, the master must transmit a memory address to identify thememory location where the slave is to store the data. the memory address is always the second byte trans- mitted during a write operation following the slave address byte. i 2 c communication writing to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and gener-ate a stop condition. remember that the master must read the slave? acknowledgement during all byte-write operations. reading from a slave: to read from the slave, the master generates a start condition, writes the slaveaddress byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generatesa stop condition. ds4402/ds4404 two/four-channel, i 2 c adjustable current dac _____________________________________________________________________ 7 sclnote: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low figure 3. i 2 c timing diagram downloaded from: http:///
ds4402/ds4404 two/four-channel, i 2 c adjustable current dac 8 ______________________________________________________________________ applications information example calculations for an adjustable power supply using the typical circuit, assuming a typical output volt-age of 2.0v, a feedback voltage of 0.8v, r1 = 500 , and r2 = 333 , to adjust or margin the supply 20% requires a full-scale current equal to [(0.2 x 2.0v) /500 = 800?]. using equation 1, r fs can be calculat- ed [r fs = (v ref / 800?) x (31 / 4) = 11.9k ]. the cur- rent dac in this configuration allows the output voltageto be stepped linearly from 1.6v to 2.4v using 63 set- tings. this corresponds to a resolution of 12.7mv/step. power-supply feedback voltage the feedback voltage for adjustable power suppliesmust be between 0.5v and v cc - 0.5v for the ds4402/ ds4404 to properly sink/source currents for adjustingthe voltage. i 2 c reset on address change in addition to defining the i 2 c slave address, the ds4402/ ds4404 address select inputs have an alternate function. changing the address select inputs resets the i 2 c inter- face. this function aborts the current transaction and putsthe sda driver into a high-impedance state. this hard- ware reset function should never be required because it is achievable through software, but it does provide an alternative way of resetting the i 2 c interface, if needed. v cc decoupling to achieve the best results when using the ds4402/ds4404, decouple the power supply with a 0.01? or 0.1? capacitor. use a high-quality ceramic surface- mount capacitor if possible. surface-mount compo- nents minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. layout considerations care should be taken to ensure that traces underneaththe ds4402/ds4404 do not short with the exposed pad. the exposed pad should be connected to the signal ground, or can be left unconnected. slave address* start start a7 a6 a5 a4 a3 a2 a1 r/w slave ack slave ack slave ack msb lsb msb lsb msb lsb b7 b6 b5 b4 b3 b2 b1 b0 read/ write register/memory address b7 b6 b5 b4 b3 b2 b1 b0 data stop single byte write-write resistor f9h to 00h single byte read-read resistor f8h start repeated start a1h master nack stop 1 0100000 11111 000 f8h 10100 001 1 0100000 11111 001 a0h f9h stop data example i 2 c transactions (when a0 and a1 are n.c.) typical i 2 c write transaction *the slave address is determined by address pins a0 and a1 (see table 1). 00000 000 a0h a)b) slave ack slave ack slave ack slave ack slave ack slave ack figure 4. i 2 c communication examples chip information transistor count: 10,992 package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . package type package code document no. 14 tdfn-ep t1433+1 21-0137 downloaded from: http:///
ds4402/ds4404 two/four-channel, i 2 c adjustable current dac heaney maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 9 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. revision history revision number revision date description pages changed 0 4/06 initial release. 1 8/06 in the featres , corrected the operating range from 1.7v to 5.5v to 2.7v to 5.5v. 1 2 10/08 added the i/o capacitance (c i/o ) parameter to the dc electrical characteristics table. 2 3 5/09 in the otpt crrent characteristics table, added v out:sink = 0.5v; v out:source = v cc = 0.8v to the i out:fs conditions. 2 downloaded from: http:///
|
